1. Field of the Invention
The present invention relates to a technology for supporting (aiding) designing a circuit in which a Programmable Logic Device (PLD) is used as a component.
2. Description of the Related Art
In designing an electrical circuit in which the PLD such as an FPGA (Field Programmable Gate Array) is used as a component, a pin assignment of the PLD in a component design may be changed in the package design. This is because, in the PLD, motion inside the component can be changed by a rewrite of a program, so that a pin replacement of the PLD is performed in a phase of the package design to perform a pin layout easily.
When a pin assignment is changed in the package design, the change of the pin assignment in the package design needs to be reflected in PLD design information to ensure a consistency of package design information and the PLD design information. Consequently, there has been developed such a technology that a pin replacement in a package design is reflected in PLD design information. For example, Japanese Patent Application Laid-open No. 2006-79447 discloses an FPGA design supporting apparatus in which information on a pin layout that is changed in a package design or a circuit design is reflected in FPGA design information.
However, there is a problem in the above FPGA design supporting apparatus such that a change of a pin layout in a package design or a circuit design can be reflected in an FPGA design, but a change of a pin layout in a package design cannot be reflected in a circuit design.